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max8791/max8791b single-phase, synchronous mosfet drivers ________________________________________________________________ maxim integrated products 1 ordering information 19-0628; rev 2; 1/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max8791/max8791b are single-phase, synchro- nous, noninverting mosfet drivers. the max8791/ max8791b are intended to work with controller ics like the max8736 or max8786, in multiphase notebook cpu core regulators. the regulators can either step down directly from the battery voltage to create the core voltage, or step down from the main system supply. the single-stage conver- sion method allows the highest possible efficiency, while the 2-stage conversion at higher switching frequency provides the minimum possible physical size. the low-side drivers are optimized to drive 3nf capaci- tive loads with 4ns/8ns typical fall/rise times, and the high-side driver with 8ns/10ns typical fall/rise times. adaptive dead-time control prevents shoot-through cur- rents and maximizes converter efficiency. the max8791/max8791b are available in a small, lead- free, 8-pin, 3mm x 3mm tqfn package. features applications + denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. part temp range pin-package max8791gta+ -40 o c to +105 o c 8 tqfn-ep* MAX8791BGTA+ -40 o c to +105 o c 8 tqfn-ep* single-phase, synchronous mosfet drivers 0.5 ? low-side on-resistance 0.7 ? high-side on-resistance 8ns propagation delay 15ns minimum guaranteed dead time integrated boost ?iode 2v to 24v input voltage range selectable pulse-skipping mode low-profile tqfn package notebooks/desktops/servers cpu core power supplies multiphase step-down converters v dd skip 12 3 65 4 8 7 pwm bst dh lx gnd dl tqfn 3mm 3mm + max8791 max8791b top view pin configuration max8791 max8791b pwm dh bst lx dl gnd pad pwm +5v bias supply skip skip v dd input (v in )* 5v to 24v v out (1.45v at 20a) typical operating circuit
max8791/max8791b single-phase, synchronous mosfet drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v dd = v skip = 5v, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd.................. -0.3v to +6v skip to gnd..................-0.3v to +6v pwm to gnd .................-0.3v to +6v dl to gnd ..................................................-0.3v to (v dd + 0.3v) bst to gnd ............................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) bst to v dd .............................................................-0.3v to +30v bst to lx ................?..-0.3v to +6v continuous power dissipation (t a = +70?) 8-pin 3mm x 3mm tqfn (derate 23.8mw/? above +70?) .............................1904mw operating temperature range .........................-40? to +105? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units input voltage range v dd 4.20 5.50 v rising edge, pwm disabled below this level 3.7 v dd undervoltage lockout threshold v uvlo ( vdd ) falling edge, pwm disabled below this level 3.0 3.5 4.0 v pwm = open; after the shutdown hold time has expired 0.08 0.2 skip = gnd, pwm = gnd, lx = gnd (after zero crossing) 0.25 0.5 quiescent supply current (v dd ) i dd skip = gnd or v dd , pwm = v dd , v bst = 5v 0.6 1.5 ma drivers t on(min) minimum on-time 50 pwm pulse width t off ( min ) minimum off-time 300 ns dl propagation delay t pwm-dl pwm high to dl low 10 ns dh propagation delay t pwm-dh pwm low to dh low 14 ns t a = 0? to +85? 15 30 dl-to-dh dead time t dl-dh dl falling to dh rising t a = -40? to +105? 15 ns t a = 0? to +85? 15 30 dh-to-dl dead time t dh-dl dh falling to dl rising t a = -40? to +105? 15 ns t f_dl falling, 3.0nf load 12 dl transition time t r_dl rising, 3.0nf load 14 ns t f_dh falling, 3.0nf load 8 dh transition time t r_dh rising, 3.0nf load 10 ns dh, high state (pullup) 0.9 2.5 dh driver on-resistance r on(dh) bst-lx forced to 5v dh, low state (pulldown) 0.7 2.3 ? dl, high state (pullup) 0.7 1.8 dl driver on-resistance r on(dl) dl, low state (pulldown) 0.5 1.2 ? d h d r i ver s our ce c ur r ent i dh_source dh forced to 2.5v, bst - lx forced to 5v 2.2 a dh driver sink current i dh_sink dh forced to 2.5v, bst - lx forced to 5v 2.7 a dl driver source current i dl_source dl forced to 2.5v 2.7 a dl driver sink current i dl_sink dl forced to 2.5v 8 a zero-crossing threshold v zx gnd - lx, skip = gnd 3 mv boost on-resistance r on ( bst ) v d d = 5v , d h = lx = g n d ( p ul l d ow n state) , i bs t = 10m a512 ?
max8791/max8791b single-phase, synchronous mosfet drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v dd = v skip = 5v, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (note 1) parameter symbol conditions min typ max units high (dh = high; dl = low) v dd - 0.4 midlevel v d d /2 - 0.4 v d d /2 + 0.4 pwm input levels low (dh = low; dl = high) 0.4 v sink; pwm forced to v dd -400 -200 -80 pwm input current i pwm source; pwm forced to gnd 80 +200 400 ? midlevel shutdown hold time t mid 120 300 600 ns rising edge 1.7 2.4 skip input threshold falling edge 0.8 1.5 v skip input current i skip sink; skip forced to 0.8v to v dd , t a = +25? -4 -2 -0.5 a thermal-shutdown threshold t shdn hysteresis = 20? +160 ? note 1: limits are 100% production tested at t a = +25?. maximum and minimum limits over temperature are guaranteed through correlation using statistical-quality-control (sqc) methods. typical operating characteristics (circuit of figure 1, v dd = 5v, c dh = 3nf, c dl = 3nf, t a = +25?, unless otherwise noted.) package-power dissipation vs. pwm frequency pwm frequency (khz) pd (mw) max8791 toc01 0 200 400 600 800 1000 1200 0 50 100 150 200 b a 250 300 a: c dh = 3.3nf; c dl = 3.3nf b: c dh = 1.5nf; c dl = 6.8nf package-power dissipation vs. capacitive load on dh and dl capacitance (pf) pd (mw) max8791 toc02 1000 2500 4000 5500 7000 8500 10,000 0 50 100 150 200 250 300 350 400 450 500 c b a a: 300khz b: 600khz c: 1mhz dl rise and fall times vs. capacitive load capacitance (pf) rise and fall time (ns) max8791 toc03 1000 2500 4000 5500 7000 8500 10,000 0 5 10 15 20 25 30 rise time fall time c dl = c dh
max8791/max8791b single-phase, synchronous mosfet drivers 4 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v dd = 5v, c dh = 3nf, c dl = 3nf, t a = +25?, unless otherwise noted.) dh rise and fall times vs. capacitive load capacitance (pf) rise and fall time (ns) max8791 toc04 1000 2500 4000 5500 7000 8500 10,000 0 5 10 15 20 25 30 35 40 rise time fall time c dl = c dh dh and dl rise and fall times vs. temperature temperature ( c) rise and fall time (ns) max8791 toc05 -40 -15 10 35 60 85 110 10 15 20 25 30 35 40 dl rise dh rise dh fall dl fall dl fall dl is driving 2 si7336adp dh is driving 1 si7892adp package-power dissipation vs. pwm frequency pwm frequency (khz) i dd (mw) max8791 toc06 0 200 400 600 800 1000 1200 0 10 20 30 40 50 60 a b a: c dh = 3.3nf; c dl = 3.3nf b: c dh = 1.5nf; c dl = 6.8nf propagation delay time vs. temperature temperature ( c) propogation delay time (ns) max8791 toc07 -40 -15 10 35 60 85 110 8 9 10 11 12 13 14 15 16 pwm fall to dh fall pwm rise to dl fall typical application circuit switching waveforms max8791 toc08 v pwm v dl 10v/div 20v/div 5v/div 5v/div 100ns/div v lx v dh dh fall and dl rise waveforms max8791 toc09 v pwm v dl 10v/div 10v/div 5v/div 5v/div 20ns/div v lx v dh dh rise and dl fall waveforms max8791 toc10 v pwm v dl 10v/div 10v/div 5v/div 5v/div 20ns/div v lx v dh
max8791/max8791b single-phase, synchronous mosfet drivers _______________________________________________________________________________________ 5 pin description pin name function 1 bst boost flying-capacitor connection. gate-drive power supply for dh high-side gate driver. connect a 0.1? or 0.22? capacitor between bst and lx. 2 pwm pwm input pin. noninverting dh control input from the controller ic: logic high: dh = high (bst), dl = low (pgnd). midlevel: after the midlevel hold time expires, the controller enters standby mode. dh and dl pulled low. logic low: dh = low (lx), dl = high (v dd ) when skip = high. internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if this input is left unconnected (not soldered properly) or driven by a high impedance. 3 gnd power ground for the dl gate drivers and analog ground. connect exposed pad to gnd. 4 dl pwm low-side gate-driver output. swings between gnd and v dd . dl forced high in shutdown. 5 v dd supply voltage input for the dl gate drivers. connect to 4.2v to 5.5v supply and bypass to gnd with a 1? ceramic capacitor. 6 skip pulse-skipping mode pin. enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is operating in skip mode: skip = v dd pwm mode skip = gnd skip mode an internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left unconnected (not soldered properly) or driven by a high impedance. 7 lx switching node and inductor connection. low-power supply for the dh high-side gate driver. lx connects to the skip-mode zero-crossing comparator. 8 dh external high-side nmosfet gate-driver output. swings between lx and bst. ep exposed pad. connect to ground through multiple vias to reduce the thermal impedance. typical operating characteristics (continued) (circuit of figure 1, v dd = 5v, c dh = 3nf, c dl = 3nf, t a = +25?, unless otherwise noted.) switching waveforms (pwm = mid to low to mid) max8791 toc11 v pwm v dl v dh v lx 0 0 0 5v 5v/div 5v/div 10v/div 0 10v/div 5v switching waveforms (pwm = high to mid to high) max8791 toc12 v pwm v dl v dh v lx 0 0 10v 0 0 5v 5v/div 5v/div 10v/div 15v 10v/div
max8791/max8791b single-phase, synchronous mosfet drivers 6 _______________________________________________________________________________________ pwm t pwm-dl dl t pwm-dh t f_dl t r_dh t r_dh t r_dh dh t dl-dh t dh-dl t mid t mid t pwm-dh t pwm-dl t f_dl t r_dl t r_dl t r_dh figure 2. timing diagram max8791 max8791b pwm dh bst lx gnd pad pwm +5v bias supply skip skip v dd c bst 0.1 f c1 1.0 f c dh 3nf dl c dl 3nf figure 1. test circuit
detail description the max8791/max8791b single-phase gate drivers, along with the max8736 or max8786 multiphase con- trollers, provide flexible multiphase cpu core-voltage supplies. the low driver resistance allows up to 7a out- put peak current. each mosfet driver in the max8791/max8791b is capable of driving 3nf capaci- tive loads with only 9ns propagation delay and 4ns/8ns (typ) fall/rise times, allowing operation up to 3mhz per phase. larger capacitive loads are allowable but result in longer propagation and transition times. adaptive dead-time control prevents shoot-through currents and maximizes converter efficiency while allowing operation with a variety of mosfets and pwm controllers. an input undervoltage lockout (uvlo) circuit allows proper power-on sequencing. pwm input the drivers for the max8791/max8791b are disabled dh and dl pulled low?f the pwm input remains in the midlevel window for at least 300ns (typ). once the pwm signal is driven high or low, the max8791/ max8791b immediately exit the low-current shutdown state and resume active operation. outside the shut- down state, the drivers are enabled based on the rising and falling thresholds specified in the electrical characteristics . mosfet gate drivers (dh, dl) the high-side driver (dh) has a 0.9 ? sourcing resis- tance and 0.7 ? sinking resistance, resulting in 2.2a peak sourcing current and 2.7a peak sinking current with a 5v supply voltage. the low-side driver (dl) has a typical 0.7 ? sourcing resistance and 0.3 ? sinking resistance, yielding 2.7a peak sourcing current and 8a peak sinking current. this reduces switching losses, making the max8791/max8791b ideal for both high- frequency and high output-current applications. max8791/max8791b single-phase, synchronous mosfet drivers _______________________________________________________________________________________ 7 output (v out ) l1 0.36 h max8791 max8791b pwm dh bst lx dl gnd pad pwm +5v bias supply skip skip v dd c bst 0.22 f c out 2x 330 f 6m ? c in 2x 10 f input (v in ) cv dd 1.0 f n l d l n h figure 3. typical mosfet-driver application circuit table 1. typical components designation qty component suppliers n h 1 per phase siliconix si4860dy n l 1? per phase siliconix si4336dy bst capacitor (c bst ) 1 per phase 0.1? or 0.22? ceramic capacitor schottky diode optional 3a, 40v schottky diode inductor (l1) 1 per phase 0.36?, 26a, 0.9m ? power inductor output capacitors (c out ) 1? per phase 330?, 6m ? per phase input capacitors (c in ) 1? per phase 10?, 25v x5r ceramic capacitors
max8791/max8791b single-phase, synchronous mosfet drivers 8 _______________________________________________________________________________________ adaptive shoot-through protection the dh and dl drivers are optimized for driving mod- erately sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. two adaptive dead-time circuits monitor the dh and dl outputs and prevent the opposite-side fet from turning on until the other is fully off. the max8791/max8791b constantly monitor the low-side driver output (dl) voltage, and only allow the high-side driver to turn on when dl drops below the adaptive threshold. similarly, the controller monitors the high-side driver output (dh), and prevents the low side from turning on until dh falls below the adaptive thresh- old before allowing dl to turn on. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimiz- ing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead- time circuits to work properly; otherwise, the sense cir- cuitry in the max8791/max8791b interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). internal boost switch the max8791/max8791b use a bootstrap circuit to generate the necessary drive voltage to fully enhance the high-side n-channel mosfet. the internal p-chan- nel mosfet creates an ideal diode, providing a low voltage drop between v dd and bst. the selected high-side mosfet determines appropriate boost capacitance values (c bst in figure 1), according to the following equation: where q gate is the total gate charge of the high-side mosfet and ? v bst is the voltage variation allowed on the high-side mosfet driver. choose ? v bst = 0.1v to 0.2v when determining c bst . the boost flying capacitor should be a low equivalent-series resistance (esr) ceramic capacitor. cq v bst gate bst =? bst dh lx v dd dl gnd uvlo lx zx detection driver logic and dead-time control pwm v dd skip drv drv# thermal shutdown pad figure 4. overview block diagram
5v bias supply (v dd ) v dd provides the supply voltage for the internal logic cir- cuits. bypass v dd with a 1? or larger ceramic capaci- tor to gnd to limit noise to the internal circuitry. connect these bypass capacitors as close as possible to the ic. input undervoltage lockout when v dd is below the uvlo threshold, dh and dl are held low. once v dd is above the uvlo threshold and while pwm is low, dl is driven high and dh is driven low. this prevents the output of the converter from rising before a valid pwm signal is applied. low-power pulse skipping the max8791/max8791b enter into low-power pulse- skipping mode when skip is pulled low. in skip mode, an inherent automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. a zero- crossing comparator truncates the low-side switch on- time at the inductor current? zero crossing. the comparator senses the voltage across lx and gnd. once v lx - v gnd drops below the zero-crossing com- parator threshold (see the electrical characteristics ), the comparator forces dl low. this mechanism causes the threshold between pulse-skipping pfm and non- skipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-cur- rent operation. the pfm/pwm crossover occurs when the load current of each phase is equal to 1/2 the peak- to-peak ripple current, which is a function of the induc- tor value. for a battery input range of 7v to 20v, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the switching waveforms may appear noisy and asynchronous when light loading activates the pulse-skipping operation, but this is a normal oper- ating condition that results in high light-load efficiency. applications information power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but increasing c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) but reducing c gate ). if v in does not vary over a wide range, the minimum power dissi- pation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d2pak), and is reasonably priced. ensure that the dl gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side mosfet turning on; otherwise, cross-con- duction problems can occur. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: where total is the total number of phases. generally, a small high-side mosfet is desired to reduce switch- ing losses at high input voltages. however, the r ds(on) required to stay within package-power dissipation often limits how small the mosfets can be. again, the opti- mum occurs when the switching losses equal the con- duction (r ds(on) ) losses. high-side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for prototype evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfet? output capacitance, q g(sw) is the charge needed to turn on the high-side mosfet, and i gate is the peak gate-drive source/sink current (5a typ). pd n switching vif n q i cvf h in max load sw total gsw gate oss in sw ( ) () () = ? ? ? ? ? ? ? ? ? ? ? ? + 2 2 pd n resistive v v i r h out in load total ds on ( ) () = ? ? ? ? ? ? ? ? ? ? ? ? 2 max8791/max8791b single-phase, synchronous mosfet drivers _______________________________________________________________________________________ 9
max8791/max8791b switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied due to the squared term in the switching-loss equation above. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at the maximum input voltage: the worst case for mosfet power dissipation occurs under heavy load conditions that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. the mosfets must have a good-sized heatsink to handle the overload power dissipation. the heat sink can be a large copper field on the pcb or an externally mounted device. an optional schottky diode only conducts during the dead time when both the high-side and low-side mosfets are off. choose a schottky diode with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time, and a peak current rating higher than the peak inductor current. the schottky diode must be rated to handle the average power dissipation per switching cycle. this diode is optional and can be removed if effi- ciency is not critical. ic power dissipation and thermal considerations power dissipation in the ic package comes mainly from driving the mosfets. therefore, it is a function of both switching frequency and the total gate charge of the selected mosfets. the total power dissipation when both drivers are switching is given by: where i bias is the bias current of the 5v supply calcu- lated in the 5v bias supply (v dd ) section. the rise in die temperature due to self-heating is given by the following formula: where pd(ic) is the power dissipated by the device, and ja is the package? thermal resistance. the typi- cal thermal resistance is 42?/w for the 3mm x 3mm tqfn package. avoiding dv/dt turning on the low-side mosfet at high input voltages, fast turn-on of the high-side mosfet can momentarily turn on the low-side mosfet due to the high dv/dt appearing at the drain of the low- side mosfet. the high dv/dt causes a current flow through the miller capacitance (c rss ) and the input capacitance (c iss ) of the low-side mosfet. improper selection of the low-side mosfet that results in a high ratio of c rss /c iss makes the problem more severe. to avoid this problem, minimize the ratio of c rss /c iss when selecting the low-side mosfet. adding a 1 ? to 4.7 ? resistor between bst and c bst can slow the high-side mosfet turn-on. similarly, adding a small capacitor from the gate to the source of the high-side mosfet has the same effect. however, both methods work at the expense of increased switching losses. layout guidelines the max8791/max8791b mosfet driver sources and sinks large currents to drive mosfets at high switch- ing speeds. the high di/dt can cause unacceptable ringing if the trace lengths and impedances are not well controlled. the following pcb layout guidelines are rec- ommended when designing with the max8791/ max8791b: 1) place all decoupling capacitors as close as possi- ble to their respective ic pins. 2) minimize the length of the high-current loop from the input capacitor, the upper switching mosfet, and the low-side mosfet back to the input-capacitor negative terminal. 3) provide enough copper area at and around the switching mosfets and inductors to aid in thermal dissipation. 4) connect gnd of the max8791/max8791b as close as possible to the source of the low-side mosfets. a sample layout is available in the max8786 evaluation kit. ? tpdic jja = () pd ic i v bias () = 5 pd n resistive v v i r l out in max load total ds on ( ) () () =? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 single-phase, synchronous mosfet drivers 10 ______________________________________________________________________________________
max8791/max8791b single-phase, synchronous mosfet drivers ______________________________________________________________________________________ 11 chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code document no. 8 tdfn-ep tq833+1 21-0136
max8791/max8791b single-phase, synchronous mosfet drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/06 initial release 1 11/06 updated electrical characteristics and pwm input section. 3, 7 2 1/10 added the max8791b to entire data sheet. 1?2

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